1. Field of the Invention
The present invention relates to an apparatus. More particularly, the present invention relates to an apparatus for detecting edges of an input signal to executes signal processing on the basis of edge timings.
2. Description of the Related Art
Edge detecting circuits are widely used for various signal processing. An edge detecting circuit is disclosed in Japanese Laid Open Patent Application (JP-A-2001 136157). The entire disclosure of the corresponding U.S. patent application Ser. No. 09/699,245, filed Oct. 27, 2000 is hereby incorporated herein in its entirety by reference. The edge detecting circuit is used in a clock signal reproducing apparatus. The clock signal reproducing apparatus is composed of a detecting circuit and a clock signal outputting circuit. The detecting circuit detects edge timings of an input signal at which the input signal is inverted. The detecting circuit quantizes the detected edge timings to a predetermined number of states. The clock signal outputting circuit outputs an outputted clock signal. A phase of the outputted clock signal is established based on the edge timings.
Another edge detecting circuit for surely detecting edges of signals is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 1-260915). As shown in FIG. 1, the conventional apparatus includes flip-flop circuits 101-104, inverters 105, 106, delay circuits 107-110, XOR gates 111-114, an OR gate 115 and an address decoder 116. The conventional apparatus detects that address signals 120, 121 are changed from the High level to the Low level or from the Low level to the High level.
When the address signal 120 is changed from the Low level to the High level as shown in FIG. 2, the flip-flop circuit 101 detects the change to generate an output pulse. Next, when the address signal 120 is changed from the High level to the Low level, the flip-flop circuit 102 detects the change. In the conventional edge detecting circuit, even if the change to the High level from the Low level is done in the time shorter than the predetermined delay time TW, a sure edge detection signal is inputted to an enable terminal of the address decoder 116 without any separation of the output pulse.
However, the conventional edge detecting circuit does not output a signal indicating edge timings of the address signals 120, 121. The conventional edge detecting circuit merely detects that the address signals 120, 121 are changed from the High level to the Low level, or from the Low level to the High level, and only sets the address decoder 116 enable.
Also, a synchronizing circuit including an edge detecting circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 4-13325). The synchronizing circuit receives a data signal, synchronizes an interior clock signal with the data signal, and samples the data signal with the synchronized clock signal. In detail, the synchronizing circuit includes a data signal edge detecting circuit, a clock signal edge detecting circuit, a synchronization judging circuit, and a clock signal selecting circuit. The data signal edge detecting circuit outputs a data signal edge detection pulse when detecting an edge of the data signal. The clock signal edge detecting circuit outputs a clock signal edge detection pulse when detecting an edge of the clock signal. The synchronization judging circuit superposes the data signal edge detection pulse and the clock signal edge detection pulse to output an asynchronous state detection pulse. The clock signal is responsive to asynchronous state detection pulse for selecting one of clock signals having different phases to output it as the interior clock signal. However, the edge timing of the data signal is not detected in the synchronizing circuit and the operation of the synchronizing circuit is not based on the edge timing.
An object of the present invention is to provide an apparatus for detecting an edge timing and operating on the basis of the edge timing while power consumption thereof is reduced.
Another object of the present invention is to provide an apparatus for detecting an edge timing and operating on the basis of the edge timing while the operation thereof is stabilized.
In order to achieve an aspect of the present invention, an apparatus includes an edge detecting circuit that detects edges of an input signal to generate an edge timing representing signal representative of edge timings of the edges, a signal processing circuit responsive to the edge timing representing signal. The edge detection circuit outputs an enable signal to enable the signal processing circuit to operate when the edge detection circuit finds one of the edges. The signal processing circuit executes a signal processing of the edge timing representing signal in response to the enable signal.
The edge detecting circuit preferably quantizes the edge timings to represent the edge timings in the edge timing representing signal.
The enable signal preferably consists of rectangular pulses having a pulse width larger than a predetermined value.
The edge detection circuit preferably detects the edges in synchronization with a clock signal, and the pulse width is larger than a cycle of the clock signal.
The edge detection circuit preferably generates the enable signal based on the edge timing representing signal.
The edge detection circuit preferably changes a state of the edge timing representing signal is changed only when the edge detection detects the edges.
The edge detecting circuit preferably includes a plurality of sampling circuits each of which is responsive to one of clock signals for sampling the input signal in synchronization with the one of the clock signals to generate a sample signal, the clock signals having different phases each other, and an edge timing determining circuit generates the edge timing representing signal based on the sample signals received from the plurality of sampling circuits, the edge timing determining circuit determining the edge timings on the basis of whether or not two of the sample signals indicate different values.
In order to achieve another aspect of the present invention, a clock signal reproducing circuit includes an edge detecting circuit which detects edges of an input signal to generate an edge timing representing signal representative of edge timings of the edges, a clock signal outputting circuit responsive to the edge timing representing signal for generating another clock signal synchronized with the input signal. The edge detection circuit outputs an enable signal to enable the clock signal outputting circuit to operate when the edge detection circuit finds one of the edges.
The clock signal outputting circuit preferably selects one of a plurality of clock signals having different phases each other on the basis of the edge timing representing signal and output the one of the plurality of clock signals as the another clock signal.
In the case when the edges have a present edge which is latest of the edges, and a past edge detected before the present edge, the clock signal outputting circuit preferably includes a memorizing circuit memorizing a past edge timing of the past edge, the another clock signal is outputted on the basis of edge timings of the present edge and the past edge.
In order to achieve still another aspect of the present invention, a signal reproducing circuit includes an edge detecting circuit which detects edges of an input signal to generate an edge timing representing signal representative of edge timings of the edges, a clock signal outputting circuit responsive to the edge timing representing signal for generating another clock signal synchronized with the input signal, and a reproduced signal outputting circuit sampling the input signal with the another clock signal to output a reproduced signal. The edge detection circuit outputs an enable signal to enable the clock signal outputting circuit to operate when the edge detection circuit finds one of the edges.
In order to achieve yet still aspect of the present invention, a method of operating an apparatus includes:
detecting edges of an input signal;
outputting an edge timing representing signal representative of edge timings of the edges;
outputting an enable signal when one of the edges is detected; and
enabling a circuit to operate in response to the edge timing representing signal.
The circuit preferably outputs a clock signal synchronized with the input signal on the basis of the edge timings.